Class | Description |
---|---|
DrcRing |
Create a ring in layers p1 and m1 - m5.
|
Inv | |
Inv_passgate |
Caution: unlike Nand gates, Jon says "LT" for Inverters means
increase the size of the NMOS rather than decrease the size of the
PMOS.
|
Inv_star_wideOutput |
run a wide output bus in metal-1 along n-well/p-well boundary
|
Inv2i | |
Inv2iKn |
Tricky: Normally the strong PMOS is folded and the right most
source/drain is ground.
|
Inv2iKp |
Tricky: Normally the strong PMOS is folded and the right most
source/drain is ground.
|
InvCLK | |
InvCTLn | |
InvHT | |
InvLT | |
InvV |
Separate control over N and P transistor sizes.
|
MoCMOSGenerator | |
MullerC_sy | |
Nand2 | |
Nand2_star_en | |
Nand2_sy | |
Nand2en | |
Nand2en_sy | |
Nand2HLT | |
Nand2HLT_sy | |
Nand2HTen | |
Nand2LT | |
Nand2LT_sy | |
Nand2LTen | |
Nand2PH | |
Nand2PHfk | |
Nand3 | |
Nand3_star_sy3 | |
Nand3_sy3 | |
Nand3en | |
Nand3en_sy | |
Nand3en_sy3 | |
Nand3LT | |
Nand3LT_sy3 | |
Nand3LTen | |
Nand3LTen_sy | |
Nand3LTen_sy3 | |
Nand3MLT | |
Nms1 | |
Nms2 | |
Nms2_sy | |
Nms3_sy3 | |
Nor2 | |
Nor2kresetV | |
Nor2LT | |
Pms1 | |
Pms2 | |
Pms2_sy | |
TieHi |
This part has an output connected to Vdd.
|
VertTrack |
This part simply reserves space for one vertical metal1 track to be
used to connect N-stacks and P-stacks.
|
WellTie |