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iverilog - Icarus Verilog is a verilog compiler and simulator

Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard.
License:GPL Group:Packages not in Groups
URL:http://www.icarus.com/eda/verilog/index.html Source: iverilog

Packages

Name Version Release Type Size Built
iverilog 0.9.20070421 1.fc6 x86_64 2.21 MiB Mon Apr 23 09:41:39 2007

Changelog

* Mon Apr 23 18:00:00 2007 Balint Cristian <cbalint{%}redhat{*}com> 0.9.20070421-1
- new snapshot release upstream.
* Tue Feb 27 17:00:00 2007 Balint Cristian <cbalint{%}redhat{*}com> 0.9.20070227-1
- new snapshoot release.
* Tue Feb 27 17:00:00 2007 Balint Cristian <cbalint{%}redhat{*}com> 0.9.20070123-5
- clean junks from tarball
- exlude static library
- smp build seems fine
- use snapshot instead of cvsver macro
- follow package n-v-r from fedora standard

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