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00023 #ifndef INCLUDED_USRP1_SINK_BASE_H
00024 #define INCLUDED_USRP1_SINK_BASE_H
00025
00026 #include <gr_sync_block.h>
00027 #include <stdexcept>
00028
00029 class usrp_standard_tx;
00030
00031
00035 class usrp1_sink_base : public gr_sync_block {
00036 private:
00037 usrp_standard_tx *d_usrp;
00038 int d_nunderruns;
00039
00040 protected:
00041 usrp1_sink_base (const std::string &name,
00042 gr_io_signature_sptr input_signature,
00043 int which_board,
00044 unsigned int interp_rate,
00045 int nchan,
00046 int mux,
00047 int fusb_block_size,
00048 int fusb_nblocks,
00049 const std::string fpga_filename,
00050 const std::string firmware_filename
00051 ) throw (std::runtime_error);
00052
00064 virtual void copy_to_usrp_buffer (gr_vector_const_void_star &input_items,
00065 int input_index,
00066 int input_items_available,
00067 int &input_items_consumed,
00068 void *usrp_buffer,
00069 int usrp_buffer_length,
00070 int &bytes_written) = 0;
00071
00072 public:
00074 static const int READ_FAILED = -99999;
00075
00076
00077 ~usrp1_sink_base ();
00078
00079 int work (int noutput_items,
00080 gr_vector_const_void_star &input_items,
00081 gr_vector_void_star &output_items);
00082
00083 bool start();
00084 bool stop();
00085
00092 bool set_interp_rate (unsigned int rate);
00093 bool set_nchannels (int nchan);
00094 bool set_mux (int mux);
00095
00103 bool set_tx_freq (int channel, double freq);
00104
00105 void set_verbose (bool verbose);
00106
00121 bool set_pga (int which, double gain_in_db);
00122
00128 double pga (int which) const;
00129
00133 double pga_min () const;
00134
00138 double pga_max () const;
00139
00143 double pga_db_per_step () const;
00144
00145
00146
00147
00148 long fpga_master_clock_freq() const;
00149 long converter_rate() const;
00150 long dac_rate() const { return converter_rate(); }
00151 long dac_freq() const { return converter_rate(); }
00152
00153 unsigned int interp_rate () const;
00154 int nchannels () const;
00155 int mux () const;
00156 double tx_freq (int channel) const;
00157 int nunderruns () const { return d_nunderruns; }
00158
00166 int daughterboard_id (int which_dboard) const;
00167
00178 bool write_aux_dac (int which_board, int which_dac, int value);
00179
00187 int read_aux_adc (int which_dboard, int which_adc);
00188
00196 bool write_eeprom (int i2c_addr, int eeprom_offset, const std::string buf);
00197
00205 std::string read_eeprom (int i2c_addr, int eeprom_offset, int len);
00206
00214 bool write_i2c (int i2c_addr, const std::string buf);
00215
00223 std::string read_i2c (int i2c_addr, int len);
00224
00230 bool set_adc_offset (int which, int offset);
00231
00239 bool set_dac_offset (int which, int offset, int offset_pin);
00240
00247 bool set_adc_buffer_bypass (int which, bool bypass);
00248
00254 std::string serial_number();
00255
00271 bool _write_oe (int which_dboard, int value, int mask);
00272
00280 bool write_io (int which_dboard, int value, int mask);
00281
00288 int read_io (int which_dboard);
00289
00290
00291
00292
00293
00300 bool _write_fpga_reg (int regno, int value);
00301
00307 int _read_fpga_reg (int regno);
00308
00316 bool _write_9862 (int which_codec, int regno, unsigned char value);
00317
00324 int _read_9862 (int which_codec, int regno) const;
00325
00339 bool _write_spi (int optional_header, int enables, int format, std::string buf);
00340
00341
00342
00343
00344
00345
00346
00347
00348
00349
00350
00351
00352
00353
00354
00355
00356 std::string _read_spi (int optional_header, int enables, int format, int len);
00357 };
00358
00359 #endif