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00039 #ifndef INCLUDED_USRP_BASIC_H
00040 #define INCLUDED_USRP_BASIC_H
00041
00042 #include <usrp_slots.h>
00043 #include <string>
00044
00045 struct usb_dev_handle;
00046 class fusb_devhandle;
00047 class fusb_ephandle;
00048
00052 class usrp_basic
00053 {
00054 private:
00055
00056 usrp_basic (const usrp_basic &rhs);
00057 usrp_basic &operator= (const usrp_basic &rhs);
00058
00059
00060 protected:
00061 struct usb_dev_handle *d_udh;
00062 int d_usb_data_rate;
00063 int d_bytes_per_poll;
00064 bool d_verbose;
00065
00066 static const int MAX_REGS = 128;
00067 unsigned int d_fpga_shadows[MAX_REGS];
00068
00069 usrp_basic (int which_board,
00070 struct usb_dev_handle *open_interface (struct usb_device *dev),
00071 const std::string fpga_filename = "",
00072 const std::string firmware_filename = "");
00073
00083 void set_usb_data_rate (int usb_data_rate);
00084
00095 bool write_aux_dac (int slot, int which_dac, int value);
00096
00105 bool read_aux_adc (int slot, int which_adc, int *value);
00106
00114 int read_aux_adc (int slot, int which_adc);
00115
00116 public:
00117 virtual ~usrp_basic ();
00118
00122 long fpga_master_clock_freq () const { return 64000000; }
00123
00127 int usb_data_rate () const { return d_usb_data_rate; }
00128
00129 void set_verbose (bool on) { d_verbose = on; }
00130
00132 static const int READ_FAILED = -99999;
00133
00141 bool write_eeprom (int i2c_addr, int eeprom_offset, const std::string buf);
00142
00150 std::string read_eeprom (int i2c_addr, int eeprom_offset, int len);
00151
00159 bool write_i2c (int i2c_addr, const std::string buf);
00160
00168 std::string read_i2c (int i2c_addr, int len);
00169
00175 bool set_adc_offset (int which, int offset);
00176
00184 bool set_dac_offset (int which, int offset, int offset_pin);
00185
00192 bool set_adc_buffer_bypass (int which, bool bypass);
00193
00194
00200 std::string serial_number();
00201
00202
00203
00204
00205
00206
00207 bool _set_led (int which, bool on);
00208
00215 bool _write_fpga_reg (int regno, int value);
00216
00223 bool _read_fpga_reg (int regno, int *value);
00224
00230 int _read_fpga_reg (int regno);
00231
00232
00241 bool _write_fpga_reg_masked (int regno, int value, int mask);
00242
00250 bool _write_9862 (int which_codec, int regno, unsigned char value);
00251
00259 bool _read_9862 (int which_codec, int regno, unsigned char *value) const;
00260
00267 int _read_9862 (int which_codec, int regno) const;
00268
00282 bool _write_spi (int optional_header, int enables, int format, std::string buf);
00283
00284
00285
00286
00287
00288
00289
00290
00291
00292
00293
00294
00295
00296
00297
00298
00299 std::string _read_spi (int optional_header, int enables, int format, int len);
00300
00305 bool start ();
00306
00311 bool stop ();
00312 };
00313
00314
00317 class usrp_basic_rx : public usrp_basic
00318 {
00319 private:
00320 fusb_devhandle *d_devhandle;
00321 fusb_ephandle *d_ephandle;
00322 int d_bytes_seen;
00323 bool d_first_read;
00324 bool d_rx_enable;
00325
00326 protected:
00327 int d_dbid[2];
00328
00335 usrp_basic_rx (int which_board,
00336 int fusb_block_size=0,
00337 int fusb_nblocks=0,
00338 const std::string fpga_filename = "",
00339 const std::string firmware_filename = ""
00340 );
00341
00342 bool set_rx_enable (bool on);
00343 bool rx_enable () const { return d_rx_enable; }
00344
00345 bool disable_rx ();
00346 void restore_rx (bool on);
00347
00348 void probe_rx_slots (bool verbose);
00349 int dboard_to_slot (int dboard) { return (dboard << 1) | 1; }
00350
00351 public:
00352 ~usrp_basic_rx ();
00353
00362 static usrp_basic_rx *make (int which_board,
00363 int fusb_block_size=0,
00364 int fusb_nblocks=0,
00365 const std::string fpga_filename = "",
00366 const std::string firmware_filename = ""
00367 );
00368
00369
00370
00380 bool set_fpga_rx_sample_rate_divisor (unsigned int div);
00381
00390 int read (void *buf, int len, bool *overrun);
00391
00392
00393
00395 virtual long converter_rate() const { return fpga_master_clock_freq(); }
00396 long adc_rate() const { return converter_rate(); }
00397 long adc_freq() const { return converter_rate(); }
00398
00408 int daughterboard_id (int which_dboard) const { return d_dbid[which_dboard & 0x1]; }
00409
00410
00411
00424 bool set_pga (int which, double gain_in_db);
00425
00431 double pga (int which) const;
00432
00436 double pga_min () const { return 0.0; }
00437
00441 double pga_max () const { return 20.0; }
00442
00446 double pga_db_per_step () const { return 20.0 / 20; }
00447
00463 bool _write_oe (int which_dboard, int value, int mask);
00464
00472 bool write_io (int which_dboard, int value, int mask);
00473
00480 bool read_io (int which_dboard, int *value);
00481
00488 int read_io (int which_dboard);
00489
00500 bool write_aux_dac (int which_board, int which_dac, int value);
00501
00510 bool read_aux_adc (int which_dboard, int which_adc, int *value);
00511
00519 int read_aux_adc (int which_dboard, int which_adc);
00520
00524 int block_size() const;
00525
00546 bool set_dc_offset_cl_enable(int bits, int mask);
00547
00548
00549 bool start ();
00550 bool stop ();
00551 };
00552
00553
00556 class usrp_basic_tx : public usrp_basic
00557 {
00558 private:
00559 fusb_devhandle *d_devhandle;
00560 fusb_ephandle *d_ephandle;
00561 int d_bytes_seen;
00562 bool d_first_write;
00563 bool d_tx_enable;
00564
00565 protected:
00566 int d_dbid[2];
00567
00574 usrp_basic_tx (int which_board,
00575 int fusb_block_size=0,
00576 int fusb_nblocks=0,
00577 const std::string fpga_filename = "",
00578 const std::string firmware_filename = ""
00579 );
00580
00581 bool set_tx_enable (bool on);
00582 bool tx_enable () const { return d_tx_enable; }
00583
00584 bool disable_tx ();
00585 void restore_tx (bool on);
00586
00587 void probe_tx_slots (bool verbose);
00588 int dboard_to_slot (int dboard) { return (dboard << 1) | 0; }
00589
00590 public:
00591
00592 ~usrp_basic_tx ();
00593
00602 static usrp_basic_tx *make (int which_board, int fusb_block_size=0, int fusb_nblocks=0,
00603 const std::string fpga_filename = "",
00604 const std::string firmware_filename = ""
00605 );
00606
00607
00608
00618 bool set_fpga_tx_sample_rate_divisor (unsigned int div);
00619
00629 int write (const void *buf, int len, bool *underrun);
00630
00631
00632
00633
00634
00635 void wait_for_completion ();
00636
00637
00638
00640 virtual long converter_rate() const { return fpga_master_clock_freq () * 2; }
00641 long dac_rate() const { return converter_rate(); }
00642 long dac_freq() const { return converter_rate(); }
00643
00651 int daughterboard_id (int which_dboard) const { return d_dbid[which_dboard & 0x1]; }
00652
00653
00654
00669 bool set_pga (int which, double gain_in_db);
00670
00676 double pga (int which) const;
00677
00681 double pga_min () const { return -20.0; }
00682
00686 double pga_max () const { return 0.0; }
00687
00691 double pga_db_per_step () const { return 20.0/255; }
00692
00708 bool _write_oe (int which_dboard, int value, int mask);
00709
00717 bool write_io (int which_dboard, int value, int mask);
00718
00725 bool read_io (int which_dboard, int *value);
00726
00733 int read_io (int which_dboard);
00734
00745 bool write_aux_dac (int which_board, int which_dac, int value);
00746
00755 bool read_aux_adc (int which_dboard, int which_adc, int *value);
00756
00764 int read_aux_adc (int which_dboard, int which_adc);
00765
00769 int block_size() const;
00770
00771
00772 bool start ();
00773 bool stop ();
00774 };
00775
00776 #endif