PIC18F86J90 | ||||
---|---|---|---|---|
CONFIG1L (address:0x00FFF8, mask:0xE1) | ||||
WDTEN -- Watchdog Timer | ||||
WDTEN = OFF | 0xFE | Disabled-Controlled by SWDTEN bit. | ||
WDTEN = ON | 0xFF | Enabled. | ||
STVREN -- Stack Overflow Reset | ||||
STVREN = OFF | 0xDF | Disabled. | ||
STVREN = ON | 0xFF | Enabled. | ||
XINST -- Extended Instruction Set Enable bit | ||||
XINST = OFF | 0xBF | Disabled. | ||
XINST = ON | 0xFF | Enabled. | ||
DEBUG -- Background Debugger Enable bit | ||||
DEBUG = ON | 0x7F | Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug. | ||
DEBUG = OFF | 0xFF | Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins. | ||
CONFIG1H (address:0x00FFF9, mask:0xF4) | ||||
CP0 -- Code Protect | ||||
CP0 = ON | 0xFB | Enabled. | ||
CP0 = OFF | 0xFF | Disabled. | ||
CONFIG2L (address:0x00FFFA, mask:0xDF) | ||||
OSC -- Oscillator Selection bits | ||||
OSC = INTOSC | 0xF8 | Internal oscillator, port function on RA6 and RA7 . | ||
OSC = INTOSCPLL | 0xF9 | INTOSC with PLL enabled, port function on RA6 and RA7. | ||
OSC = INTOSCO | 0xFA | Internal oscillator, CLKOUT on RA6 and port function on RA7. | ||
OSC = INTOSCPLLO | 0xFB | INTOSC with PLL enabled, CLKOUT on RA6 and port function on RA7. | ||
OSC = HS | 0xFC | HS oscillator. | ||
OSC = HSPLL | 0xFD | HS oscillator, PLL enabled. | ||
OSC = EC | 0xFE | EC Oscillator with clock out on RA6. | ||
OSC = ECPLL | 0xFF | EC Oscillator with PLL. | ||
T1DIG -- Secondary Clock Source T1OSCEN Enforcement | ||||
T1DIG = OFF | 0xF7 | Secondary Oscillator clock source may not be selected. | ||
T1DIG = ON | 0xFF | Secondary Oscillator clock source may be selected. | ||
LPT1OSC -- Low-Power Timer1 Oscillator Enable bit | ||||
LPT1OSC = ON | 0xEF | Timer1 oscillator configured for low-power operation. | ||
LPT1OSC = OFF | 0xFF | Timer1 oscillator configured for higher power operation. | ||
FCMEN -- Fail-Safe Clock Monitor Enable bit | ||||
FCMEN = OFF | 0xBF | Fail-Safe Clock Monitor disabled. | ||
FCMEN = ON | 0xFF | Fail-Safe Clock Monitor enabled. | ||
IESO -- Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit | ||||
IESO = OFF | 0x7F | Two-Speed Start-up disabled. | ||
IESO = ON | 0xFF | Two-Speed Start-up enabled. | ||
CONFIG2H (address:0x00FFFB, mask:0xFF) | ||||
WDTPS -- Watchdog Timer Postscaler Select bits | ||||
WDTPS = 1 | 0xF0 | 1:1. | ||
WDTPS = 2 | 0xF1 | 1:2. | ||
WDTPS = 4 | 0xF2 | 1:4. | ||
WDTPS = 8 | 0xF3 | 1:8. | ||
WDTPS = 16 | 0xF4 | 1:16. | ||
WDTPS = 32 | 0xF5 | 1:32. | ||
WDTPS = 64 | 0xF6 | 1:64. | ||
WDTPS = 128 | 0xF7 | 1:128. | ||
WDTPS = 256 | 0xF8 | 1:256. | ||
WDTPS = 512 | 0xF9 | 1:512. | ||
WDTPS = 1024 | 0xFA | 1:1024. | ||
WDTPS = 2048 | 0xFB | 1:2048. | ||
WDTPS = 4096 | 0xFC | 1:4096. | ||
WDTPS = 8192 | 0xFD | 1:8192. | ||
WDTPS = 16384 | 0xFE | 1:16384. | ||
WDTPS = 32768 | 0xFF | 1:32768. | ||
CONFIG3L (address:0x00FFFC, mask:0xF2) | ||||
RTCSOSC -- RTCC Reference Clock Select bit | ||||
RTCSOSC = INTOSCREF | 0xFD | RTCC uses INTOSC/INTRC as reference clock. | ||
RTCSOSC = T1OSCREF | 0xFF | RTCC uses T1OSC/T1CKI as reference clock. | ||
CONFIG3H (address:0x00FFFD, mask:0xF1) | ||||
CCP2MX -- CCP2 MUX | ||||
CCP2MX = ALTERNATE | 0xFE | RE7. | ||
CCP2MX = DEFAULT | 0xFF | RC1. |
This page generated automatically by the device-help.pl program (2014-05-17 13:45:47 UTC) from the 8bit_device.info file (rev: 1.19) of mpasmx and from the gputils source package (rev: svn 1017). The mpasmx is included in the MPLAB X.