00001 /* 00002 ----------------------------------------------------------------------------- 00003 This source file is part of OGRE 00004 (Object-oriented Graphics Rendering Engine) 00005 For the latest info, see http://www.ogre3d.org/ 00006 00007 Copyright (c) 2000-2006 Torus Knot Software Ltd 00008 Also see acknowledgements in Readme.html 00009 00010 This program is free software; you can redistribute it and/or modify it under 00011 the terms of the GNU Lesser General Public License as published by the Free Software 00012 Foundation; either version 2 of the License, or (at your option) any later 00013 version. 00014 00015 This program is distributed in the hope that it will be useful, but WITHOUT 00016 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 00017 FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details. 00018 00019 You should have received a copy of the GNU Lesser General Public License along with 00020 this program; if not, write to the Free Software Foundation, Inc., 59 Temple 00021 Place - Suite 330, Boston, MA 02111-1307, USA, or go to 00022 http://www.gnu.org/copyleft/lesser.txt. 00023 00024 You may alternatively use this source under the terms of a specific version of 00025 the OGRE Unrestricted License provided you have obtained such a license from 00026 Torus Knot Software Ltd. 00027 ----------------------------------------------------------------------------- 00028 */ 00029 #ifndef __SIMDHelper_H__ 00030 #define __SIMDHelper_H__ 00031 00032 #include "OgrePrerequisites.h" 00033 #include "OgrePlatformInformation.h" 00034 00035 // Stack-alignment hackery. 00036 // 00037 // If macro __OGRE_SIMD_ALIGN_STACK defined, means there requests 00038 // special code to ensure stack align to a 16-bytes boundary. 00039 // 00040 // Note: 00041 // This macro can only guarantee callee stack pointer (esp) align 00042 // to a 16-bytes boundary, but not that for frame pointer (ebp). 00043 // Because most compiler might use frame pointer to access to stack 00044 // variables, so you need to wrap those alignment required functions 00045 // with extra function call. 00046 // 00047 #if defined(__INTEL_COMPILER) 00048 // For intel's compiler, simply calling alloca seems to do the right 00049 // thing. The size of the allocated block seems to be irrelevant. 00050 #define __OGRE_SIMD_ALIGN_STACK() _alloca(16) 00051 00052 #elif OGRE_CPU == OGRE_CPU_X86 && OGRE_COMPILER == OGRE_COMPILER_GNUC 00053 // 00054 // Horrible hack to align the stack to a 16-bytes boundary for gcc. 00055 // 00056 // We assume a gcc version >= 2.95 so that 00057 // -mpreferred-stack-boundary works. Otherwise, all bets are 00058 // off. However, -mpreferred-stack-boundary does not create a 00059 // stack alignment, but it only preserves it. Unfortunately, 00060 // since Ogre are designed as a flexibility library, user might 00061 // compile their application with wrong stack alignment, even 00062 // if user taken care with stack alignment, but many versions 00063 // of libc on linux call main() with the wrong initial stack 00064 // alignment the result that the code is now pessimally aligned 00065 // instead of having a 50% chance of being correct. 00066 // 00067 #if OGRE_ARCH_TYPE != OGRE_ARCHITECTURE_64 00068 00069 #define __OGRE_SIMD_ALIGN_STACK() \ 00070 { \ 00071 /* Use alloca to allocate some memory on the stack. */ \ 00072 /* This alerts gcc that something funny is going on, */ \ 00073 /* so that it does not omit the frame pointer etc. */ \ 00074 (void)__builtin_alloca(16); \ 00075 /* Now align the stack pointer */ \ 00076 __asm__ __volatile__ ("andl $-16, %esp"); \ 00077 } 00078 00079 #else // 64 00080 #define __OGRE_SIMD_ALIGN_STACK() \ 00081 { \ 00082 /* Use alloca to allocate some memory on the stack. */ \ 00083 /* This alerts gcc that something funny is going on, */ \ 00084 /* so that it does not omit the frame pointer etc. */ \ 00085 (void)__builtin_alloca(16); \ 00086 /* Now align the stack pointer */ \ 00087 __asm__ __volatile__ ("andq $-16, %rsp"); \ 00088 } 00089 #endif //64 00090 00091 #elif defined(_MSC_VER) 00092 // Fortunately, MSVC will align the stack automatically 00093 00094 #endif 00095 00096 00097 // Additional platform-dependent header files and declares. 00098 // 00099 // NOTE: Should be sync with __OGRE_HAVE_SSE macro. 00100 // 00101 00102 #if OGRE_DOUBLE_PRECISION == 0 && OGRE_CPU == OGRE_CPU_X86 00103 00104 #if OGRE_COMPILER == OGRE_COMPILER_MSVC || defined(__INTEL_COMPILER) 00105 #include <xmmintrin.h> 00106 00107 #elif OGRE_COMPILER == OGRE_COMPILER_GNUC 00108 // Don't define ourself version SSE intrinsics if "xmmintrin.h" already included. 00109 // 00110 // Note: gcc in some platform already included "xmmintrin.h" for some reason. 00111 // I pick up macro _XMMINTRIN_H_INCLUDED here which based on the "xmmintrin.h" 00112 // comes with cygwin gcc 3.4.4, guess it should be solved duplicate definition 00113 // problem on gcc for x86. 00114 // 00115 #if !defined(_XMMINTRIN_H_INCLUDED) 00116 00117 // Simulate VC/ICC intrinsics. Only used intrinsics are declared here. 00118 00119 typedef float __m128 __attribute__ ((mode(V4SF),aligned(16))); 00120 typedef int __m64 __attribute__ ((mode(V2SI))); 00121 00122 // Macro for declare intrinsic routines always inline even if in debug build 00123 #define __ALWAYS_INLINE FORCEINLINE __attribute__ ((__always_inline__)) 00124 00125 // Shuffle instruction must be declare as macro 00126 00127 #define _MM_SHUFFLE(fp3,fp2,fp1,fp0) \ 00128 (((fp3) << 6) | ((fp2) << 4) | ((fp1) << 2) | ((fp0))) 00129 00130 #define _mm_shuffle_ps(a, b, imm8) __extension__ \ 00131 ({ \ 00132 __m128 result; \ 00133 __asm__("shufps %3, %2, %0" : "=x" (result) : "0" (a), "xm" (b), "N" (imm8)); \ 00134 result; \ 00135 }) 00136 00137 00138 // Load/store instructions 00139 00140 #define __MM_DECL_LD(name, instruction, type) \ 00141 static __ALWAYS_INLINE __m128 _mm_##name(const type *addr) \ 00142 { \ 00143 __m128 result; \ 00144 __asm__( #instruction " %1, %0" : "=x" (result) : "m" (*addr)); \ 00145 return result; \ 00146 } 00147 00148 #define __MM_DECL_LD2(name, instruction, type) \ 00149 static __ALWAYS_INLINE __m128 _mm_##name(__m128 val, const type *addr) \ 00150 { \ 00151 __m128 result; \ 00152 __asm__( #instruction " %2, %0" : "=x" (result) : "0"(val), "m" (*addr)); \ 00153 return result; \ 00154 } 00155 00156 #define __MM_DECL_ST(name, instruction, type) \ 00157 static __ALWAYS_INLINE void _mm_##name(type *addr, __m128 val) \ 00158 { \ 00159 __asm__( #instruction " %1, %0" : "=m" (*addr) : "x" (val)); \ 00160 } 00161 00162 __MM_DECL_LD(loadu_ps, movups, float) 00163 __MM_DECL_ST(storeu_ps, movups, float) 00164 00165 __MM_DECL_LD(load_ss, movss, float) 00166 __MM_DECL_ST(store_ss, movss, float) 00167 00168 __MM_DECL_ST(storel_pi, movlps, __m64) 00169 __MM_DECL_ST(storeh_pi, movhps, __m64) 00170 __MM_DECL_LD2(loadl_pi, movlps, __m64) 00171 __MM_DECL_LD2(loadh_pi, movhps, __m64) 00172 00173 #undef __MM_DECL_LD 00174 #undef __MM_DECL_LD2 00175 #undef __MM_DECL_ST 00176 00177 // Two operand instructions 00178 00179 #define __MM_DECL_OP2(name, instruction, constraint) \ 00180 static __ALWAYS_INLINE __m128 _mm_##name(__m128 a, __m128 b) \ 00181 { \ 00182 __m128 result; \ 00183 __asm__( #instruction " %2, %0" : "=x" (result) : "0" (a), #constraint (b)); \ 00184 return result; \ 00185 } 00186 00187 __MM_DECL_OP2(add_ps, addps, xm) 00188 __MM_DECL_OP2(add_ss, addss, xm) 00189 __MM_DECL_OP2(sub_ps, subps, xm) 00190 __MM_DECL_OP2(sub_ss, subss, xm) 00191 __MM_DECL_OP2(mul_ps, mulps, xm) 00192 __MM_DECL_OP2(mul_ss, mulss, xm) 00193 00194 __MM_DECL_OP2(xor_ps, xorps, xm) 00195 00196 __MM_DECL_OP2(unpacklo_ps, unpcklps, xm) 00197 __MM_DECL_OP2(unpackhi_ps, unpckhps, xm) 00198 00199 __MM_DECL_OP2(movehl_ps, movhlps, x) 00200 __MM_DECL_OP2(movelh_ps, movlhps, x) 00201 00202 __MM_DECL_OP2(cmpnle_ps, cmpnleps, xm) 00203 00204 #undef __MM_DECL_OP2 00205 00206 // Other used instructions 00207 00208 static __ALWAYS_INLINE __m128 _mm_load_ps1(const float *addr) 00209 { 00210 __m128 tmp = _mm_load_ss(addr); 00211 return _mm_shuffle_ps(tmp, tmp, 0); 00212 } 00213 00214 static __ALWAYS_INLINE __m128 _mm_setzero_ps(void) 00215 { 00216 __m128 result; 00217 __asm__("xorps %0, %0" : "=x" (result)); 00218 return result; 00219 } 00220 00221 static __ALWAYS_INLINE __m128 _mm_rsqrt_ps(__m128 val) 00222 { 00223 __m128 result; 00224 __asm__("rsqrtps %1, %0" : "=x" (result) : "xm" (val)); 00225 //__asm__("rsqrtps %0, %0" : "=x" (result) : "0" (val)); 00226 return result; 00227 } 00228 00229 static __ALWAYS_INLINE int _mm_movemask_ps(__m128 val) 00230 { 00231 int result; 00232 __asm__("movmskps %1, %0" : "=r" (result) : "x" (val)); 00233 return result; 00234 } 00235 00236 #endif // !defined(_XMMINTRIN_H_INCLUDED) 00237 00238 #endif // OGRE_COMPILER == OGRE_COMPILER_GNUC 00239 00240 #endif // OGRE_DOUBLE_PRECISION == 0 && OGRE_CPU == OGRE_CPU_X86 00241 00242 00243 00244 //--------------------------------------------------------------------- 00245 // SIMD macros and helpers 00246 //--------------------------------------------------------------------- 00247 00248 00249 namespace Ogre { 00250 00251 #if __OGRE_HAVE_SSE 00252 00263 #if 1 00264 #define __MM_RSQRT_PS(x) _mm_rsqrt_ps(x) 00265 #else 00266 #define __MM_RSQRT_PS(x) __mm_rsqrt_nr_ps(x) // Implemented below 00267 #endif 00268 00277 #define __MM_TRANSPOSE4x4_PS(r0, r1, r2, r3) \ 00278 { \ 00279 __m128 t3, t2, t1, t0; \ 00280 \ 00281 /* r00 r01 r02 r03 */ \ 00282 /* r10 r11 r12 r13 */ \ 00283 /* r20 r21 r22 r23 */ \ 00284 /* r30 r31 r32 r33 */ \ 00285 \ 00286 t0 = _mm_unpacklo_ps(r0, r1); /* r00 r10 r01 r11 */ \ 00287 t2 = _mm_unpackhi_ps(r0, r1); /* r02 r12 r03 r13 */ \ 00288 t1 = _mm_unpacklo_ps(r2, r3); /* r20 r30 r21 r31 */ \ 00289 t3 = _mm_unpackhi_ps(r2, r3); /* r22 r32 r23 r33 */ \ 00290 \ 00291 r0 = _mm_movelh_ps(t0, t1); /* r00 r10 r20 r30 */ \ 00292 r1 = _mm_movehl_ps(t1, t0); /* r01 r11 r21 r31 */ \ 00293 r2 = _mm_movelh_ps(t2, t3); /* r02 r12 r22 r32 */ \ 00294 r3 = _mm_movehl_ps(t3, t2); /* r03 r13 r23 r33 */ \ 00295 } 00296 00305 #define __MM_TRANSPOSE4x3_PS(v0, v1, v2) \ 00306 { \ 00307 __m128 t0, t1, t2; \ 00308 \ 00309 /* r00 r01 r02 r10 */ \ 00310 /* r11 r12 r20 r21 */ \ 00311 /* r22 r30 r31 r32 */ \ 00312 \ 00313 t0 = _mm_shuffle_ps(v0, v2, _MM_SHUFFLE(3,0,3,0)); /* r00 r10 r22 r32 */ \ 00314 t1 = _mm_shuffle_ps(v0, v1, _MM_SHUFFLE(1,0,2,1)); /* r01 r02 r11 r12 */ \ 00315 t2 = _mm_shuffle_ps(v1, v2, _MM_SHUFFLE(2,1,3,2)); /* r20 r21 r30 r31 */ \ 00316 \ 00317 v0 = _mm_shuffle_ps(t0, t2, _MM_SHUFFLE(2,0,1,0)); /* r00 r10 r20 r30 */ \ 00318 v1 = _mm_shuffle_ps(t1, t2, _MM_SHUFFLE(3,1,2,0)); /* r01 r11 r21 r31 */ \ 00319 v2 = _mm_shuffle_ps(t1, t0, _MM_SHUFFLE(3,2,3,1)); /* r02 r12 r22 r32 */ \ 00320 } 00321 00329 #define __MM_TRANSPOSE3x4_PS(v0, v1, v2) \ 00330 { \ 00331 __m128 t0, t1, t2; \ 00332 \ 00333 /* r00 r10 r20 r30 */ \ 00334 /* r01 r11 r21 r31 */ \ 00335 /* r02 r12 r22 r32 */ \ 00336 \ 00337 t0 = _mm_shuffle_ps(v0, v2, _MM_SHUFFLE(2,0,3,1)); /* r10 r30 r02 r22 */ \ 00338 t1 = _mm_shuffle_ps(v1, v2, _MM_SHUFFLE(3,1,3,1)); /* r11 r31 r12 r32 */ \ 00339 t2 = _mm_shuffle_ps(v0, v1, _MM_SHUFFLE(2,0,2,0)); /* r00 r20 r01 r21 */ \ 00340 \ 00341 v0 = _mm_shuffle_ps(t2, t0, _MM_SHUFFLE(0,2,2,0)); /* r00 r01 r02 r10 */ \ 00342 v1 = _mm_shuffle_ps(t1, t2, _MM_SHUFFLE(3,1,2,0)); /* r11 r12 r20 r21 */ \ 00343 v2 = _mm_shuffle_ps(t0, t1, _MM_SHUFFLE(3,1,1,3)); /* r22 r30 r31 r32 */ \ 00344 } 00345 00349 #define __MM_SELECT(v, fp) \ 00350 _mm_shuffle_ps((v), (v), _MM_SHUFFLE((fp),(fp),(fp),(fp))) 00351 00353 #define __MM_ACCUM4_PS(a, b, c, d) \ 00354 _mm_add_ps(_mm_add_ps(a, b), _mm_add_ps(c, d)) 00355 00359 #define __MM_DOT4x4_PS(a0, a1, a2, a3, b0, b1, b2, b3) \ 00360 __MM_ACCUM4_PS(_mm_mul_ps(a0, b0), _mm_mul_ps(a1, b1), _mm_mul_ps(a2, b2), _mm_mul_ps(a3, b3)) 00361 00365 #define __MM_DOT4x3_PS(r0, r1, r2, r3, v0, v1, v2) \ 00366 __MM_ACCUM4_PS(_mm_mul_ps(r0, v0), _mm_mul_ps(r1, v1), _mm_mul_ps(r2, v2), r3) 00367 00369 #define __MM_ACCUM3_PS(a, b, c) \ 00370 _mm_add_ps(_mm_add_ps(a, b), c) 00371 00375 #define __MM_DOT3x3_PS(r0, r1, r2, v0, v1, v2) \ 00376 __MM_ACCUM3_PS(_mm_mul_ps(r0, v0), _mm_mul_ps(r1, v1), _mm_mul_ps(r2, v2)) 00377 00379 #define __MM_MADD_PS(a, b, c) \ 00380 _mm_add_ps(_mm_mul_ps(a, b), c) 00381 00383 #define __MM_LERP_PS(t, a, b) \ 00384 __MM_MADD_PS(_mm_sub_ps(b, a), t, a) 00385 00387 #define __MM_MADD_SS(a, b, c) \ 00388 _mm_add_ss(_mm_mul_ss(a, b), c) 00389 00391 #define __MM_LERP_SS(t, a, b) \ 00392 __MM_MADD_SS(_mm_sub_ss(b, a), t, a) 00393 00395 #define __MM_LOAD_PS(p) \ 00396 (*(__m128*)(p)) 00397 00399 #define __MM_STORE_PS(p, v) \ 00400 (*(__m128*)(p) = (v)) 00401 00402 00405 template <bool aligned = false> 00406 struct SSEMemoryAccessor 00407 { 00408 static FORCEINLINE __m128 load(const float *p) 00409 { 00410 return _mm_loadu_ps(p); 00411 } 00412 static FORCEINLINE void store(float *p, const __m128& v) 00413 { 00414 _mm_storeu_ps(p, v); 00415 } 00416 }; 00417 // Special aligned accessor 00418 template <> 00419 struct SSEMemoryAccessor<true> 00420 { 00421 static FORCEINLINE const __m128& load(const float *p) 00422 { 00423 return __MM_LOAD_PS(p); 00424 } 00425 static FORCEINLINE void store(float *p, const __m128& v) 00426 { 00427 __MM_STORE_PS(p, v); 00428 } 00429 }; 00430 00433 static FORCEINLINE bool _isAlignedForSSE(const void *p) 00434 { 00435 return (((size_t)p) & 15) == 0; 00436 } 00437 00441 static FORCEINLINE __m128 __mm_rsqrt_nr_ps(const __m128& x) 00442 { 00443 static const __m128 v0pt5 = { 0.5f, 0.5f, 0.5f, 0.5f }; 00444 static const __m128 v3pt0 = { 3.0f, 3.0f, 3.0f, 3.0f }; 00445 __m128 t = _mm_rsqrt_ps(x); 00446 return _mm_mul_ps(_mm_mul_ps(v0pt5, t), 00447 _mm_sub_ps(v3pt0, _mm_mul_ps(_mm_mul_ps(x, t), t))); 00448 } 00449 00450 // Macro to check the stack aligned for SSE 00451 #if OGRE_DEBUG_MODE 00452 #define __OGRE_CHECK_STACK_ALIGNED_FOR_SSE() \ 00453 { \ 00454 __m128 test; \ 00455 assert(_isAlignedForSSE(&test)); \ 00456 } 00457 00458 #else // !OGRE_DEBUG_MODE 00459 #define __OGRE_CHECK_STACK_ALIGNED_FOR_SSE() 00460 00461 #endif // OGRE_DEBUG_MODE 00462 00463 00464 #endif // __OGRE_HAVE_SSE 00465 00466 } 00467 00468 #endif // __SIMDHelper_H__
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Last modified Tue Nov 4 11:02:34 2008